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Technologies & Domain

RASPBERRY PI Technology & LOW POWER DESIGN Domain Projects

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VLP1301 Low Power and Area Efficient Carry Select Adder
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VLP1302 Eliminating Synchronization Latency Using Sequenced Latching
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VLP1303 Mapping Loop Structures onto Parameterized Hardware Pipelines
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VLP1304 Low Power Pulse Triggered Flip Flop Design With Conditional Pulse Enhancement Scheme
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VLP1305 Low Power Dual Dynamic Node Pulsed Hybrid Flip Flop Featuring Efficient Embedded Logic
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VLP1306 A High Speed Low Power CAM With a Parity Bit and Power Gated ML Sensing
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VLP1307 Performance analysis of low power 1bit CMOS full adder cells
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VLP1308 Low Cost FIR Filter Designs Based on Faithfully Rounded Truncated Multiple Constant Multiplication Accumulation
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VLP1309 Area Efficient ROM Embedded SRAM Cache
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VLP1310 Efficient VLSI Implementation of 2n Scaling of Signed Integer in RNS 2n 1 2n 2n 1
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